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Stage-by-Stage Power Gating Circuit for Ultra-Low-Power Self-Timed Pipeline

Shuji Sannomiya, Kei Miyagi, Makoto Iwata, Hiroaki Nishikawa. Stage-by-Stage Power Gating Circuit for Ultra-Low-Power Self-Timed Pipeline. In Hamid R. Arabnia, Steve C. Chiu, George A. Gravvanis, Minoru Ito, Kazuki Joe, Hiroaki Nishikawa, Ashu M. G. Solo, editors, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2010, Las Vegas, Nevada, USA, July 12-15, 2010, 2 Volumes. pages 596-602, CSREA Press, 2010.

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