The following publications are possibly variants of this publication:
- Multi-FPGA Accelerator for Scalable Stencil Computation with Constant Memory BandwidthKentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto. tpds, 25(3):695-705, 2014. [doi]
- Domain-specific programmable design of scalable streaming-array for power-efficient stencil computationKentaro Sano, Satoru Yamamoto, Yoshiaki Hatsuda. sigarch, 39(4):44-49, 2011. [doi]
- Prototype implementation of array-processor extensible over multiple FPGAs for scalable stencil computationKentaro Sano, Luzhou Wang, Satoru Yamamoto. sigarch, 38(4):80-86, 2010. [doi]
- Domain-Specific Language and Compiler for Stencil Computation on FPGA-Based Systolic Computational-Memory ArrayLuzhou Wang, Kentaro Sano, Satoru Yamamoto. arc 2012: 26-39 [doi]