Abstract is missing.
- A Sparse Matrix Personality for the Convey HC-1Krishna K. Nagar, Jason D. Bakos. 1-8 [doi]
- Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional VerificationLingkan Gong, Oliver Diessel. 9-16 [doi]
- Mixed Precision Processing in Reconfigurable SystemsGary Chun Tak Chow, K. W. Kwok, Wayne Luk, Philip Leong. 17-24 [doi]
- Dynamic Communication in a Coarse Grained Reconfigurable ArrayRobin Panda, Scott Hauck. 25-28 [doi]
- Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable ProcessorsWaheed Ahmed, Muhammad Shafique, Lars Bauer, Manuel Hammerich, Jörg Henkel, Jürgen Becker. 29-32 [doi]
- An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAsJainik Kathiara, Miriam Leeser. 33-36 [doi]
- Hecto-Scale Frame Rate Face Detection System for SVGA Source on FPGA BoardZheng-ding, Feng Zhao, Tinghui Wang, Wei Shu, Min-You Wu. 37-40 [doi]
- An FPGA Implementation of Information Theoretic Visual-Saliency System and Its OptimizationSungmin Bae, Yong Cheol Peter Cho, Sungho Park, Kevin M. Irick, Yongseok Jin, Vijaykrishnan Narayanan. 41-48 [doi]
- Scalable, High Performance Fourier Domain Optical Coherence Tomography: Why FPGAs and Not GPGPUsJian Li, Marinko Sarunic, Lesley Shannon. 49-56 [doi]
- Architecture, Design, and Experimental Evaluation of a Lightfield Descriptor Depth Buffer Algorithm on Reconfigurable Logic and on a GPUMatina Lakka, Grigorios Chrysos, Ioannis Papaefstathiou, Apostolos Dollas. 57-64 [doi]
- Implementation and Performance Analysis of SEAL Encryption on FPGA, GPU and Multi-core ProcessorsKostas Theoharoulis, Charalambos Antoniadis, Nikolaos Bellas, Christos D. Antonopoulos. 65-68 [doi]
- FPGA Communication FrameworkPeter Lieber, Brad L. Hutchings. 69-72 [doi]
- Efficient Calculation of Pairwise Nonbonded ForcesMatt Chiu, Md. Ashfaquzzaman Khan, Martin C. Herbordt. 73-76 [doi]
- High Performance IP Lookup on FPGA with Combined Length-Infix Pipelined SearchYi-Hua Edward Yang, Oguzhan Erdem, Viktor K. Prasanna. 77-80 [doi]
- A Scalable Multi-FPGA Platform for Complex Networking ApplicationsSascha Mühlbach, Andreas Koch. 81-84 [doi]
- An FPGA-Based Optical IOH Architecture for Embedded SystemLiu Ling, Jincan Zhuang, Qianying Zhu, Shunyu Zhu, Zhiyuan Zhang, Xinxin Zhang, Lu Cao, Zhihong Yu, Xiangbin Wu, Dong Liu. 85-88 [doi]
- On Comparing Financial Option Price Solvers on FPGAQiwei Jin, Wayne Luk, David B. Thomas. 89-92 [doi]
- Low-Latency FPGA Based Financial Data Feed HandlerRobin Pottathuparambil, Jack Coyne, Jeffrey Allred, William Lynch, Vincent Natoli. 93-96 [doi]
- Design and Implementation of an FPGA-Based Real-Time Face Recognition SystemJanarbek Matai, Ali Irturk, Ryan Kastner. 97-100 [doi]
- FPGA-Based Solid-State Drive Prototyping PlatformYu Cai, Erich F. Haratsch, Mark McCartney, Ken Mai. 101-104 [doi]
- Accelerating Statistical LOR Estimation for a High-Resolution PET Scanner Using FPGA Devices and a High Level Synthesis ToolZhong-Ho Chen, Alvin Wen-Yu Su, Ming-Ting Sun, Scott Hauck. 105-108 [doi]
- SYSCORE: A Coarse Grained Reconfigurable Array Architecture for Low Energy Biosignal ProcessingKunjan Patel, Séamas McGettrick, Chris J. Bleakley. 109-112 [doi]
- High-Throughput, Lossless Data Compresion on FPGAsBharat Sukhwani, Bülent Abali, Bernard Brezzo, Sameh W. Asaad. 113-116 [doi]
- HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid PrototypingChristopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings. 117-124 [doi]
- Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAsSebastian Korf, Dario Cozzi, Markus Koester, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert, Marco D. Santambrogio. 125-132 [doi]
- Using Functional Programming to Generate an LDPC Forward Error CorrectorAndy Gill, Tristan Bull, Dan DePardo, Andrew Farmer, Ed Komp, Erik Perrins. 133-140 [doi]
- Reconfigurable Data Processing for CloudsAnil Madhavapeddy, Satnam Singh. 141-145 [doi]
- TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory SystemNehir Sönmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero. 146-153 [doi]
- The PowerPC 405 Memory Sentinel and Injection SystemMark Bucciero, John Paul Walters, Roger Moussalli, Shanyuan Gao, Matthew French. 154-161 [doi]
- Checkpoint/Restart and Beyond: Resilient High Performance Computing with FPGAsAndrew G. Schmidt, Bin Huang, Ron Sass, Matthew French. 162-169 [doi]
- FUSE: Front-End User Framework for O/S Abstraction of Hardware AcceleratorsAws Ismail, Lesley Shannon. 170-177 [doi]
- Multilevel Granularity Parallelism Synthesis on FPGAsAlexandros Papakonstantinou, Yun Liang, John A. Stratton, Karthik Gururaj, Deming Chen, Wen-mei W. Hwu, Jason Cong. 178-185 [doi]
- Synthesis of Platform Architectures from OpenCL ProgramsMuhsen Owaida, Nikolaos Bellas, Konstantis Daloukas, Christos D. Antonopoulos. 186-193 [doi]
- Programming Real-Time Autofocus on a Massively Parallel Reconfigurable Architecture Using Occam-piZain-ul-Abdin, Anders Ahlander, Bertil Svensson. 194-201 [doi]
- Towards Synthesis-Free JIT Compilation to Commodity FPGAsDavor Capalija, Tarek S. Abdelrahman. 202-205 [doi]
- Automated Placement for Parallelized FPGA FFTsSuraj Gowda, Aaron Parsons, Robert Jarnot, Dan Werthimer. 206-209 [doi]
- Reducing the Energy Cost of Irregular Code Bases in Soft Processor SystemsManish Arora, Jack Sampson, Nathan Goulding-Hotta, Jonathan Babb, Ganesh Venkatesh, Michael Bedford Taylor, Steven Swanson. 210-213 [doi]
- Extending Force-Directed Scheduling with Explicit Parallel and Timed Constructs for High-Level SynthesisRohit Sinha, Hiren D. Patel. 214-217 [doi]
- String Matching in Hardware Using the FM-IndexEdward Fernandez, Walid Najjar, Stefano Lonardi. 218-225 [doi]
- Accelerating Phylogeny-Aware Short DNA Read Alignment with FPGAsNikolaos Alachiotis, Simon A. Berger, Alexandros Stamatakis. 226-233 [doi]
- Scalable Streaming-Array of Simple Soft-Processors for Stencil Computations with Constant Memory-BandwidthKentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto. 234-241 [doi]
- Memory-Efficient IPv4/v6 Lookup on FPGAs Using Distance-Bounded Path CompressionHoang Le, Weirong Jiang, Viktor K. Prasanna. 242-249 [doi]
- A Key Size Configurable High Speed RSA CoprocessorEmilio Castillo, Javier Castillo, Javier Cano, Pablo Huerta, José Ignacio Martínez. 250 [doi]
- A Model for Peak Matrix Performance on FPGAsColin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong. 251 [doi]
- Reconsideration of Computing Paradigms and a Novel Reconfigurable ArchitectureMing Yan, Ziyu Yang, Sikun Li, Liu Yang. 252 [doi]
- Hybrid Data Structure for IP Lookup in Virtual Routers Using FPGAsOguzhan Erdem, Hoang Le, Viktor K. Prasanna, Cüneyt F. Bazlamaçci. 253 [doi]
- FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking ActivitiesWill X. Y. Li, Ray C. C. Cheung, Wei Zhang, Rosa H. M. Chan, Dong Song, Theodore W. Berger. 254 [doi]
- Implementation and Performance Comparison of the Motion Compensation Kernel of the AVS Video Decoder on FPGA, GPU and Multicore ProcessorsMuhsen Owaida, Nikolaos Bellas, Christos D. Antonopoulos, Konstantis Daloukas, Charalambos Antoniadis, Konstantinos Krommydas, G. Tsoumblekas. 255 [doi]