Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors - researchr publication related

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Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano. Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. In Martin Danek, Jiri Kadlec, Brent E. Nelson, editors, 19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic. pages 530-533, IEEE, 2009. [doi]

The following publications are possibly variants of this publication:

Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating techniqueYoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano. fpt 2008: 329-332 [doi]

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