32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays

Alessio Santiccioli, Mario Mercandelli, Simone Mattia Dartizio, Francesco Tesolin, Saleh Karman, Abanob Shehata, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Dmytro Cherniak, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino. 32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. In IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021. pages 456-458, IEEE, 2021. [doi]

@inproceedings{SanticcioliMDTK21,
  title = {32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays},
  author = {Alessio Santiccioli and Mario Mercandelli and Simone Mattia Dartizio and Francesco Tesolin and Saleh Karman and Abanob Shehata and Luca Bertulessi and Francesco Buccoleri and Luca Avallone and Angelo Parisi and Dmytro Cherniak and Andrea L. Lacaita and Michael Peter Kennedy and Carlo Samori and Salvatore Levantino},
  year = {2021},
  doi = {10.1109/ISSCC42613.2021.9365972},
  url = {https://doi.org/10.1109/ISSCC42613.2021.9365972},
  researchr = {https://researchr.org/publication/SanticcioliMDTK21},
  cites = {0},
  citedby = {0},
  pages = {456-458},
  booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021},
  publisher = {IEEE},
  isbn = {978-1-7281-9549-0},
}