A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits

Sayandeep Sanyal, Amit Patra, Pallab Dasgupta, Mayukh Bhattacharya. A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits. In 28th IEEE Asian Test Symposium, ATS 2019, Kolkata, India, December 10-13, 2019. pages 135-140, IEEE, 2019. [doi]

@inproceedings{SanyalPDB19,
  title = {A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits},
  author = {Sayandeep Sanyal and Amit Patra and Pallab Dasgupta and Mayukh Bhattacharya},
  year = {2019},
  doi = {10.1109/ATS47505.2019.00025},
  url = {https://doi.org/10.1109/ATS47505.2019.00025},
  researchr = {https://researchr.org/publication/SanyalPDB19},
  cites = {0},
  citedby = {0},
  pages = {135-140},
  booktitle = {28th IEEE Asian Test Symposium, ATS 2019, Kolkata, India, December 10-13, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-2695-1},
}