An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture

Santanu Sarkar 0002, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee. An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. In International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA. pages 149-152, IEEE, 2008. [doi]

Abstract

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