On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits

Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. In International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA. pages 2761-2764, IEEE, 2008. [doi]

Abstract

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