An FPGA Architecture for ASIC-FPGA Co-design to Streamline Processing of IDSs

Tomoaki Sato, Sorawat Chivapreecha, Phichet Moungnoul, Kohji Higuchi. An FPGA Architecture for ASIC-FPGA Co-design to Streamline Processing of IDSs. In Waleed W. Smari, Joseph Natarian, editors, 2016 International Conference on Collaboration Technologies and Systems, CTS 2016, Orlando, FL, USA, October 31 - November 4, 2016. pages 412-417, IEEE Computer Society, 2016. [doi]

@inproceedings{SatoCMH16,
  title = {An FPGA Architecture for ASIC-FPGA Co-design to Streamline Processing of IDSs},
  author = {Tomoaki Sato and Sorawat Chivapreecha and Phichet Moungnoul and Kohji Higuchi},
  year = {2016},
  doi = {10.1109/CTS.2016.0079},
  url = {http://dx.doi.org/10.1109/CTS.2016.0079},
  researchr = {https://researchr.org/publication/SatoCMH16},
  cites = {0},
  citedby = {0},
  pages = {412-417},
  booktitle = {2016 International Conference on Collaboration Technologies and Systems, CTS 2016, Orlando, FL, USA, October 31 - November 4, 2016},
  editor = {Waleed W. Smari and Joseph Natarian},
  publisher = {IEEE Computer Society},
  isbn = {978-1-5090-2300-4},
}