ASIC hardware implementations for 512-bit hash function Whirlpool

Akashi Satoh. ASIC hardware implementations for 512-bit hash function Whirlpool. In International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA. pages 2917-2920, IEEE, 2008. [doi]

@inproceedings{Satoh08,
  title = {ASIC hardware implementations for 512-bit hash function Whirlpool},
  author = {Akashi Satoh},
  year = {2008},
  doi = {10.1109/ISCAS.2008.4542068},
  url = {http://dx.doi.org/10.1109/ISCAS.2008.4542068},
  researchr = {https://researchr.org/publication/Satoh08},
  cites = {0},
  citedby = {0},
  pages = {2917-2920},
  booktitle = {International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA},
  publisher = {IEEE},
}