Device and Circuit Level Design, Characterization and Implementation of Low Power 7T SRAM Cell using Heterojunction Tunneling Transistors with Oxide Overlap - researchr publication

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B. V. V. Satyanarayana, Matta Durga Prakash. Device and Circuit Level Design, Characterization and Implementation of Low Power 7T SRAM Cell using Heterojunction Tunneling Transistors with Oxide Overlap. Microprocessors and Microsystems, 77:103164, 2020. [doi]

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