Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy

Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar. Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy. In 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013. pages 356-361, IEEE, 2013. [doi]

Authors

Yogesh Dilip Save

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H. Narayanan

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Sachin B. Patkar

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