Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar. Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy. In 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013. pages 356-361, IEEE, 2013. [doi]
@inproceedings{SaveNP13-0,
title = {Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy},
author = {Yogesh Dilip Save and H. Narayanan and Sachin B. Patkar},
year = {2013},
doi = {10.1109/VLSID.2013.214},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2013.214},
researchr = {https://researchr.org/publication/SaveNP13-0},
cites = {0},
citedby = {0},
pages = {356-361},
booktitle = {26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013},
publisher = {IEEE},
isbn = {978-1-4673-4639-9},
}