Jan Schat. Simulation of SoCs with embedded mixed-signal Cores using a Verilog High-Speed Virtual Serial Interface. In 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006. pages 878-881, IEEE, 2006. [doi]
@inproceedings{Schat06,
title = {Simulation of SoCs with embedded mixed-signal Cores using a Verilog High-Speed Virtual Serial Interface},
author = {Jan Schat},
year = {2006},
doi = {10.1109/ICECS.2006.379929},
url = {http://dx.doi.org/10.1109/ICECS.2006.379929},
researchr = {https://researchr.org/publication/Schat06},
cites = {0},
citedby = {0},
pages = {878-881},
booktitle = {13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006},
publisher = {IEEE},
isbn = {1-4244-0395-2},
}