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Provably Correct Hardware Compilation using Timing Diagrams

Michael Schenke, Michael Dossis. Provably Correct Hardware Compilation using Timing Diagrams. In Jianping Wu, Samuel T. Chanson, Qiang Gao, editors, Formal Methods for Protocol Engineering and Distributed Systems, FORTE XII / PSTV XIX 99, IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XII) and Protocol Specifica. Volume 156 of IFIP Conference Proceedings, pages 313-331, Kluwer, 1999.

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