Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes

Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini. Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes. IEEE Trans. VLSI Syst., 29(4):677-690, 2021. [doi]

@article{SchiavoneRMGSWY21,
  title = {Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes},
  author = {Pasquale Davide Schiavone and Davide Rossi and Alfio Di Mauro and Frank K. Gürkaynak and Timothy Saxe and Mao Wang and Ket Chong Yap and Luca Benini},
  year = {2021},
  doi = {10.1109/TVLSI.2021.3058162},
  url = {https://doi.org/10.1109/TVLSI.2021.3058162},
  researchr = {https://researchr.org/publication/SchiavoneRMGSWY21},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. VLSI Syst.},
  volume = {29},
  number = {4},
  pages = {677-690},
}