Latency-Optimized Force-directed Process Mapping for MPSoC Architectures

Timo Schönwald, Benjamin Ranft, Oliver Bringmann, Wolfgang Rosenstiel. Latency-Optimized Force-directed Process Mapping for MPSoC Architectures. In Jens Brandt, Klaus Schneider, editors, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, March 5-7, 2012. pages 145-156, Verlag Dr. Kovac, 2012.

@inproceedings{SchonwaldRBR12,
  title = {Latency-Optimized Force-directed Process Mapping for MPSoC Architectures},
  author = {Timo Schönwald and Benjamin Ranft and Oliver Bringmann and Wolfgang Rosenstiel},
  year = {2012},
  researchr = {https://researchr.org/publication/SchonwaldRBR12},
  cites = {0},
  citedby = {0},
  pages = {145-156},
  booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, March 5-7, 2012},
  editor = {Jens Brandt and Klaus Schneider},
  publisher = {Verlag Dr. Kovac},
}