A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration

Franz Marcus Schüffny, Sebastian Höppner, Alexander Oefelein, Christian Mayr. A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration. In IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019. pages 1-5, IEEE, 2019. [doi]

Abstract

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