An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS - researchr publication

researchr

You are not signed in
Sign in
Sign up

Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro. An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS. IEICE Transactions, 96-C(6):820-827, 2013. [doi]

Abstract is missing.

runs on WebDSL