Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty. TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems, 36(4):655-668, 2017. [doi]
@article{SenguptaBM17-0,
title = {TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis},
author = {Anirban Sengupta and Saumya Bhadauria and Saraju P. Mohanty},
year = {2017},
doi = {10.1109/TCAD.2016.2597232},
url = {http://dx.doi.org/10.1109/TCAD.2016.2597232},
researchr = {https://researchr.org/publication/SenguptaBM17-0},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {36},
number = {4},
pages = {655-668},
}