Anirban Sengupta, Deepak Kachave. Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016. pages 75-80, IEEE, 2016. [doi]
Abstract is missing.