A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend

Hyeongmin Seo, Jiyun Han, Kyungmin Kim, Baek-Jin Lim, Eunseok Shin, Youngdon Choi, Hyungjong Ko, Jung Hwan Choi, Sang Hyun Lee, Changsik Yoo, Jaeduk Han. A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend. IEEE Trans. Circuits Syst. II Express Briefs, 70(2):411-415, February 2023. [doi]

Authors

Hyeongmin Seo

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Jiyun Han

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Kyungmin Kim

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Baek-Jin Lim

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Eunseok Shin

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Youngdon Choi

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Hyungjong Ko

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Jung Hwan Choi

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Sang Hyun Lee

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Changsik Yoo

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Jaeduk Han

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