sat in Digital 65 nm CMOS Using Dummy-Prefilled Microstrip Lines

Munkyo Seo, Basanth Jagannathan, John Pekarik, Mark J. W. Rodwell. sat in Digital 65 nm CMOS Using Dummy-Prefilled Microstrip Lines. J. Solid-State Circuits, 44(12):3410-3421, 2009. [doi]

@article{SeoJPR09,
  title = {sat in Digital 65 nm CMOS Using Dummy-Prefilled Microstrip Lines},
  author = {Munkyo Seo and Basanth Jagannathan and John Pekarik and Mark J. W. Rodwell},
  year = {2009},
  doi = {10.1109/JSSC.2009.2032273},
  url = {https://doi.org/10.1109/JSSC.2009.2032273},
  researchr = {https://researchr.org/publication/SeoJPR09},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {44},
  number = {12},
  pages = {3410-3421},
}