Chang-Kyung Seong, Seung Woo Lee, Woo-Young Choi. A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]
@inproceedings{SeongLC06,
title = {A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution},
author = {Chang-Kyung Seong and Seung Woo Lee and Woo-Young Choi},
year = {2006},
doi = {10.1109/ISCAS.2006.1693034},
url = {http://dx.doi.org/10.1109/ISCAS.2006.1693034},
researchr = {https://researchr.org/publication/SeongLC06},
cites = {0},
citedby = {0},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece},
publisher = {IEEE},
}