Chang-Kyung Seong, Seung Woo Lee, Woo-Young Choi. A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]
Abstract is missing.