Estimating circuit delays in FPGAs after technology mapping

Berg Severens, Elias Vansteenkiste, Karel Heyse, Dirk Stroobandt. Estimating circuit delays in FPGAs after technology mapping. In 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015. pages 1-4, IEEE, 2015. [doi]

Authors

Berg Severens

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Elias Vansteenkiste

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Karel Heyse

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Dirk Stroobandt

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