A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 µm CMOS

Mahdi Shabany, Dimpesh Patel, P. Glenn Gulak. A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 µm CMOS. IEEE Trans. on Circuits and Systems, 60-I(2):327-340, 2013. [doi]

Abstract

Abstract is missing.