Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher - researchr publication authors

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Shivani Shah, Vaibhavi Mathur, Sahithi Meenakshi Vutakuru, Kavya Borra, Nanditha P. Rao. Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher. In Francesco Leporati, Salvatore Vitabile, Amund Skavhaug, editors, 24th Euromicro Conference on Digital System Design, DSD 2021, Palermo, Spain, September 1-3, 2021. pages 97-100, IEEE, 2021. [doi]

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