Time-area efficient multiplier-free filter architectures for FPGA implementation

Mohammad Shajaan, Karsten Nielsen, John Aasted Sørensen. Time-area efficient multiplier-free filter architectures for FPGA implementation. In 1995 International Conference on Acoustics, Speech, and Signal Processing, ICASSP '95, Detroit, Michigan, USA, May 08-12, 1995. pages 3251-3254, IEEE Computer Society, 1995. [doi]

@inproceedings{ShajaanNS95,
  title = {Time-area efficient multiplier-free filter architectures for FPGA implementation},
  author = {Mohammad Shajaan and Karsten Nielsen and John Aasted Sørensen},
  year = {1995},
  doi = {10.1109/ICASSP.1995.479578},
  url = {http://doi.ieeecomputersociety.org/10.1109/ICASSP.1995.479578},
  researchr = {https://researchr.org/publication/ShajaanNS95},
  cites = {0},
  citedby = {0},
  pages = {3251-3254},
  booktitle = {1995 International Conference on Acoustics, Speech, and Signal Processing, ICASSP '95, Detroit, Michigan, USA, May 08-12, 1995},
  publisher = {IEEE Computer Society},
  isbn = {0-7803-2431-5},
}