基于等价关系的完全确定时序逻辑电路状态化简算法 (State Reduction Algorithm for Completely Specified Sequential Logic Circuit Based on Equivalence Relation)

Ao Shang, Xiaopeng Pei, Yingchun Lv, Zehua Chen. 基于等价关系的完全确定时序逻辑电路状态化简算法 (State Reduction Algorithm for Completely Specified Sequential Logic Circuit Based on Equivalence Relation). 计算机科学, 45(1):118-121, 2018. [doi]

Abstract

Abstract is missing.