Reduction of the Weight-Decay Rate of Volatile Memory Synapses in an Analog Hardware Neural Network for Accurate and Scalable On-Chip Learning - researchr publication authors

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Janak Sharda, Nilabjo Dey, Ankesh Jain, Debanjan Bhowmik. Reduction of the Weight-Decay Rate of Volatile Memory Synapses in an Analog Hardware Neural Network for Accurate and Scalable On-Chip Learning. In Thomas E. Potok, Catherine D. Schuman, editors, Proceedings of the International Conference on Neuromorphic Systems, ICONS 2020, Oak Ridge, Tennessee, USA, July, 2020. ACM, 2020. [doi]

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