Iterative and Fully Pipelined High Throughput Efficient Architectures of AES in FPGA and ASIC

Vijay K. Sharma, Saurabh Kumar, K. K. Mahapatra. Iterative and Fully Pipelined High Throughput Efficient Architectures of AES in FPGA and ASIC. Journal of Circuits, Systems, and Computers, 25(5), 2016. [doi]

Abstract

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