Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design - researchr publication

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Anjali Sharma, Harsh Sohal, Harsimran Jit Kaur. Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design. Journal of Circuits, Systems, and Computers, 28(12):1950197, 2019. [doi]

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