Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers

Ahmed Shebaita, Yehea I. Ismail. Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers. IEEE Trans. on Circuits and Systems, 55-II(1):21-25, 2008. [doi]

@article{ShebaitaI08,
  title = {Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers},
  author = {Ahmed Shebaita and Yehea I. Ismail},
  year = {2008},
  doi = {10.1109/TCSII.2007.907784},
  url = {http://dx.doi.org/10.1109/TCSII.2007.907784},
  researchr = {https://researchr.org/publication/ShebaitaI08},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on Circuits and Systems},
  volume = {55-II},
  number = {1},
  pages = {21-25},
}