Design of a Switch-Level Analog Model for Verilog

Thomas J. Sheffler. Design of a Switch-Level Analog Model for Verilog. In 2008 IEEE International Behavioral Modeling and Simulation Workshop, BMAS 2008, San Jose, CA, USA, September 25-26, 2008. pages 118-123, IEEE, 2008. [doi]

Abstract

Abstract is missing.