Abbas Sheibanyrad, Alain Greiner. Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures. In Johan Vounckx, Nadine Azémard, Philippe Maurine, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings. Volume 4148 of Lecture Notes in Computer Science, pages 191-202, Springer, 2006. [doi]
@inproceedings{SheibanyradG06,
title = {Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures},
author = {Abbas Sheibanyrad and Alain Greiner},
year = {2006},
doi = {10.1007/11847083_19},
url = {http://dx.doi.org/10.1007/11847083_19},
tags = {architecture},
researchr = {https://researchr.org/publication/SheibanyradG06},
cites = {0},
citedby = {0},
pages = {191-202},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings},
editor = {Johan Vounckx and Nadine Azémard and Philippe Maurine},
volume = {4148},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {3-540-39094-4},
}