Design of 50 MHz PLL using indigenous SCL 180 nm CMOS Technology - researchr publication

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Chandra Shekhar 0006, Shafi Qureshi. Design of 50 MHz PLL using indigenous SCL 180 nm CMOS Technology. In IEEE International Symposium on Smart Electronic Systems, iSES 2021, Jaipur, India, December 18-22, 2021. pages 12-17, IEEE, 2021. [doi]

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