A 12-Bit 31.1UW 1MS/S SAR ADC with On-Chip Input-Signal-Independent Calibration Achieving 100.4DB SFDR Using 256FF Sampling Capacitance

Junhua Shen, Akira Shikata, Anping Liu, Frederick Chalifoux. A 12-Bit 31.1UW 1MS/S SAR ADC with On-Chip Input-Signal-Independent Calibration Achieving 100.4DB SFDR Using 256FF Sampling Capacitance. In 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018. pages 91-92, IEEE, 2018. [doi]

@inproceedings{ShenSLC18,
  title = {A 12-Bit 31.1UW 1MS/S SAR ADC with On-Chip Input-Signal-Independent Calibration Achieving 100.4DB SFDR Using 256FF Sampling Capacitance},
  author = {Junhua Shen and Akira Shikata and Anping Liu and Frederick Chalifoux},
  year = {2018},
  doi = {10.1109/VLSIC.2018.8502325},
  url = {https://doi.org/10.1109/VLSIC.2018.8502325},
  researchr = {https://researchr.org/publication/ShenSLC18},
  cites = {0},
  citedby = {0},
  pages = {91-92},
  booktitle = {2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018},
  publisher = {IEEE},
  isbn = {978-1-5386-4214-6},
}