Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain - researchr publication authors

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S. M. Yasser Sherazi, Peter Nilsson, Omer Can Akgun, Henrik Sjöland, Joachim Neves Rodrigues. Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain. In International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil. pages 837-840, IEEE, 2011. [doi]

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