Weiwei Shi, Chiu-sing Choy. A 0.4V 320Mb/s 28.7µW 1024-bit configurable multiplier for subthreshold SOC encryption. In Karan S. Bhatia, Massimo Alioto, Danella Zhao, Andrew Marshall, Ramalingam Sridhar, editors, 29th IEEE International System-on-Chip Conference, SOCC 2016, Seattle, WA, USA, September 6-9, 2016. pages 125-128, IEEE, 2016. [doi]
@inproceedings{ShiC16-8,
title = {A 0.4V 320Mb/s 28.7µW 1024-bit configurable multiplier for subthreshold SOC encryption},
author = {Weiwei Shi and Chiu-sing Choy},
year = {2016},
doi = {10.1109/SOCC.2016.7905451},
url = {http://dx.doi.org/10.1109/SOCC.2016.7905451},
researchr = {https://researchr.org/publication/ShiC16-8},
cites = {0},
citedby = {0},
pages = {125-128},
booktitle = {29th IEEE International System-on-Chip Conference, SOCC 2016, Seattle, WA, USA, September 6-9, 2016},
editor = {Karan S. Bhatia and Massimo Alioto and Danella Zhao and Andrew Marshall and Ramalingam Sridhar},
publisher = {IEEE},
isbn = {978-1-5090-1367-8},
}