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-99dBc/Hz@10kHz 1MHz-step dual-loop integer-N PLL with anti-mislocking frequency calibration for global navigation satellite system receiver

Congyin Shi, Chuan Wang, Le Ye, Huailin Liao. -99dBc/Hz@10kHz 1MHz-step dual-loop integer-N PLL with anti-mislocking frequency calibration for global navigation satellite system receiver. In International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil. pages 1876-1879, IEEE, 2011. [doi]

Authors

Congyin Shi

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Chuan Wang

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Le Ye

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Huailin Liao

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