Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang. Simulation Acceleration with HW Re-Compilation Avoidance. In 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India. pages 487-491, IEEE Computer Society, 2008. [doi]
Abstract is missing.