A 32-bit microprocessor with high performance bit-map manipulation instructions

Toru Shimizu, Shunichi Iwata, Yuichi Saito, Toyohiko Yoshida, Masahito Matsuo, Junichi Hinata, Kazunori Saito. A 32-bit microprocessor with high performance bit-map manipulation instructions. In Computer Design: VLSI in Computers and Processors, ICCD 1989. Proceedings., 1989 IEEE International Conference on, Cambridge, MA, USA, October 2-4, 1989. pages 406-409, IEEE, 1989. [doi]

Authors

Toru Shimizu

This author has not been identified. Look up 'Toru Shimizu' in Google

Shunichi Iwata

This author has not been identified. Look up 'Shunichi Iwata' in Google

Yuichi Saito

This author has not been identified. Look up 'Yuichi Saito' in Google

Toyohiko Yoshida

This author has not been identified. Look up 'Toyohiko Yoshida' in Google

Masahito Matsuo

This author has not been identified. Look up 'Masahito Matsuo' in Google

Junichi Hinata

This author has not been identified. Look up 'Junichi Hinata' in Google

Kazunori Saito

This author has not been identified. Look up 'Kazunori Saito' in Google