Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule

Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto. Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule. IEICE Transactions, 89-A(12):3602-3612, 2006. [doi]

Abstract

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