The following publications are possibly variants of this publication:
- In-Hardware Training Chip Based on CMOS Invertible Logic for Machine LearningNaoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu. tcas, 67-I(5):1541-1550, 2020. [doi]
- FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible LogicDuckgyu Shin, Naoya Onizawa, Takahiro Hanyu. icecsys 2019: 115-116 [doi]
- Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible LogicNaoya Onizawa, Duckgyu Shin, Takahiro Hanyu. flap, 7(1):41-58, 2020. [doi]