Kazuya Shinozuka. A Graph Approach to Two-Level Logic Minimization. In Hamid R. Arabnia, Minyi Guo, Laurence Tianruo Yang, editors, Proceedings of the International Conference on Embedded Systems and Applications, ESA 04 & Proceedings of the International Conference on VLSI, VLSI 04, June 21-24, 2004, Las Vegas, Nevada, USA. pages 485-490, CSREA Press, 2004.
@inproceedings{Shinozuka04,
title = {A Graph Approach to Two-Level Logic Minimization},
author = {Kazuya Shinozuka},
year = {2004},
tags = {graph-rewriting, logic, rewriting logic, rewriting, systematic-approach},
researchr = {https://researchr.org/publication/Shinozuka04},
cites = {0},
citedby = {0},
pages = {485-490},
booktitle = {Proceedings of the International Conference on Embedded Systems and Applications, ESA 04 & Proceedings of the International Conference on VLSI, VLSI 04, June 21-24, 2004, Las Vegas, Nevada, USA},
editor = {Hamid R. Arabnia and Minyi Guo and Laurence Tianruo Yang},
publisher = {CSREA Press},
isbn = {1-932415-41-6},
}