Rahul Shrestha, Roy Paily. Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding. In 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013. pages 86-91, IEEE, 2013. [doi]
@inproceedings{ShresthaP13-0,
title = {Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding},
author = {Rahul Shrestha and Roy Paily},
year = {2013},
doi = {10.1109/VLSID.2013.168},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2013.168},
researchr = {https://researchr.org/publication/ShresthaP13-0},
cites = {0},
citedby = {0},
pages = {86-91},
booktitle = {26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013},
publisher = {IEEE},
isbn = {978-1-4673-4639-9},
}