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Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding

Rahul Shrestha, Roy Paily. Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding. In 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013. pages 86-91, IEEE, 2013. [doi]

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