Improving Model Checking Stateful Timed CSP with non-Zenoness through Clock-Symmetry Reduction - researchr publication authors

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Yuanjie Si, Jun Sun 0001, Yang Liu, Ting Wang. Improving Model Checking Stateful Timed CSP with non-Zenoness through Clock-Symmetry Reduction. In Lindsay Groves, Jing Sun 0002, editors, Formal Methods and Software Engineering - 15th International Conference on Formal Engineering Methods, ICFEM 2013, Queenstown, New Zealand, October 29 - November 1, 2013, Proceedings. Volume 8144 of Lecture Notes in Computer Science, pages 182-198, Springer, 2013. [doi]

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