Improving Model Checking Stateful Timed CSP with non-Zenoness through Clock-Symmetry Reduction

Yuanjie Si, Jun Sun 0001, Yang Liu, Ting Wang. Improving Model Checking Stateful Timed CSP with non-Zenoness through Clock-Symmetry Reduction. In Lindsay Groves, Jing Sun 0002, editors, Formal Methods and Software Engineering - 15th International Conference on Formal Engineering Methods, ICFEM 2013, Queenstown, New Zealand, October 29 - November 1, 2013, Proceedings. Volume 8144 of Lecture Notes in Computer Science, pages 182-198, Springer, 2013. [doi]

@inproceedings{Si0LW13,
  title = {Improving Model Checking Stateful Timed CSP with non-Zenoness through Clock-Symmetry Reduction},
  author = {Yuanjie Si and Jun Sun 0001 and Yang Liu and Ting Wang},
  year = {2013},
  doi = {10.1007/978-3-642-41202-8_13},
  url = {http://dx.doi.org/10.1007/978-3-642-41202-8_13},
  researchr = {https://researchr.org/publication/Si0LW13},
  cites = {0},
  citedby = {0},
  pages = {182-198},
  booktitle = {Formal Methods and Software Engineering - 15th International Conference on Formal Engineering Methods, ICFEM 2013, Queenstown, New Zealand, October 29 - November 1, 2013, Proceedings},
  editor = {Lindsay Groves and Jing Sun 0002},
  volume = {8144},
  series = {Lecture Notes in Computer Science},
  publisher = {Springer},
  isbn = {978-3-642-41201-1},
}